Latch

ABSTRACT

A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and a biasing circuit, for providing a biasing current to the amplifying circuit, and providing the second biasing current to the latching unit. The biasing circuit includes: a first biasing module for providing a third biasing circuit to the amplifying circuit in the first state; and a second biasing module, for providing a fourth biasing current to the amplified circuit; wherein the first biasing circuit is equal to a sum of the third biasing current and the fourth biasing current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a latch, and more particularly, to alatch capable of being operated in a high frequency.

2. Description of the Related Art

In an integrated circuit, clock signals having different frequencies areoften utilized to perform different operations. As is known, the phaselocked loop (PLL)/synthesizer is widely used for generating theabove-mentioned clock signals having different frequencies.

As known by those skilled in the art, the PLL/synthesizer comprises afrequency divider, which is utilized to divide the frequency generatedby the inner VCO (voltage controlled oscillator). Through theabove-mentioned mechanism, the PLL can output a clock signal having awanted frequency.

In general, the frequency divider is often implemented by D-typeflip-flops. Please refer to FIG. 1, which is a diagram of a frequencydivider 100 having a divisor 2 according to the prior art. As shown inFIG. 1, the frequency divider 100 is implemented by a D-type flip-flop200. The input end Q′ and the input end D of the D-type flip-flop 200are coupled to each other. In this way, as shown in FIG. 1, thefrequency of the output signal outputted from the output end Q′ is twiceof that of the clock signal CK inputted into the clock input end. Sincethe operation and function of the D-type flip-flop are well known, andthus omitted here.

In addition, the frequency divider is often operated in a highfrequency. Therefore, in the actual implementation, the D-type flip-flopis often implemented by a current mode logic (CML) circuit, whichcomprises two latches. Please note, the related theory and theconventional circuit structure can be referred to the page 290 of RFMicroelectronics (ISBN: 0-13-887571-5) written by Behzad Razavi, andfurther illustration is omitted here.

However, if the function of the above-mentioned frequency divider 100should be achieved, the input end and the output end of theabove-mentioned D-type flip-flop are coupled together such that thefeedback loop (it is equivalent to the feedback loop from the output endQ to the input end D shown in FIG. 1) is established. As mentionedpreviously, the CML D-type flip-flop is more appropriate for thehigh-frequency operation, but it still has many restrictions.

For example, if the circuit designer wants to design a frequency dividerhaving a devisor 4, the most frequently-used method is to connect twofrequency divider having a devisor 2 (that is, to connect two D-typeflip-flops).

But, if the frequency divider having the devisor 4 should be operated ina high frequency, a conventional solution is to reduce the inner load(it could be a resistor or passive device) of the D-type flip-flops suchthat the RC constant is also reduced. However, a larger biasing currentis needed such that enough signal amplitude is provided to the followingD-type flip-flop.

Please note, the operation of raising the biasing current oftenencounters following problems:

The first solution is to raise the biasing current without adjusting theW/L ratio of inner transistors. But this reduces the voltage differenceV_(DS) of the biasing current source (such as a current mirror), and mayfurther make the biasing current source be in the triode region suchthat the current cannot be increased more, and the operational frequencycannot be raised, either.

The second solution is to raise the biasing current with adjusting theW/L ratio of inner transistors. However, this makes the parasiticcapacitor of the gate of the inner transistors larger. Unfortunately,the increasing parasitic capacitor becomes the load of the previousD-type flip-flop such that the RC delay of the previous D-type flip-flopincreases accordingly. This also limits the operational frequency of theentire circuit.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the invention isto provide a latch capable of being operated in a high frequency, tofurther solve the above-mentioned problems.

According to an embodiment of the present invention, a latch isdisclosed. The latch comprises: an amplifying circuit, for receiving afirst biasing current in a first state to amplify an input signal togenerate an amplified signal; a latching unit, coupled to the amplifyingcircuit, for latching the amplified signal and for receiving a secondbiasing current in a second state to output the amplified signal; and abiasing circuit, coupled to the amplifying circuit and the latchingunit, for providing the first biasing current to the amplified circuitin the first state and for providing the second biasing current to thelatching unit, the biasing circuit comprising: a first biasing module,coupled to the amplifying circuit, for providing a third biasing currentto the amplifying circuit in the first state; and a second biasingmodule, coupled to the amplified circuit, for providing a fourth biasingcurrent to the amplifying circuit; wherein the first biasing current isequal to a sum of the third biasing current and the fourth biasingcurrent.

According to another embodiment of the present invention, a latch isdisclosed. The latch comprises: an input circuit, for receiving an inputsignal and generating an output signal according to the input signal andan input reference current; an output circuit, coupled to the inputcircuit, for receiving the output signal and outputting the outputsignal according to an output reference current; and a currentgenerating circuit, coupled to the input circuit and the output circuit,for generating the output reference current to the input circuitaccording to a clock signal, and for generating the output referencecurrent to the output circuit, the current generating circuitcomprising: a first current generating unit, for providing a firstcurrent to the input circuit when the clock signal corresponds to afirst logic level, wherein the first current is a part of the inputreference current; and a second current generating unit, for providing asecond current to the input circuit when the clock signal corresponds tothe first logic level, and for providing the second current to theoutput circuit when the clock signal corresponds to a second logiclevel, wherein the second current is a part of the input referencecurrent, and the second current is equal to the output reference currentor is a part of the output reference current.

The present invention does not need to adjust the W/L ratio of the innertransistors or to increase V_(GS) of the inner transistors in order toincrease the biasing current. Therefore, the present invention latch canprevent from the parasitic capacitor problem and can be operated in ahigh frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a frequency divider having a divisor 2 accordingto the prior art.

FIG. 2 is a diagram of a latch of a first embodiment according to thepresent invention.

FIG. 3 is a diagram showing the control clock CK and the inversedcontrol clock CKN.

FIG. 4 is a diagram of a latch of a first embodiment according to thepresent invention.

FIG. 5 is a diagram of a latch of a third embodiment according to thepresent invention.

FIG. 6 is a diagram of a latch of a fourth embodiment according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The “TITLE” of the invention will be described with reference to theaccompanying drawings.

Please refer to FIG. 2, which is a diagram of a latch 400 of a firstembodiment according to the present invention. As shown in FIG. 2, thelatch 200 comprises a preamplifier 410, a latching unit 420, and abiasing circuit 430.

The latching unit 420 comprises two cross-coupled transistors M5 and M6.Because the gate of the transistor M5 is coupled to the drain of thetransistor M6 and the gate of transistor M6 is coupled to the drain ofthe transistor M5 (cross-coupling structure), the signals Von and Vopcan be utilized to control the conducting conditions of the transistorsM5 and M6 such that the voltage level of the signals Von and Vop can bemaintained.

Please note, the biasing circuit 430 in the latch 400 is different fromthe conventional biasing circuit. In this embodiment, the biasingcircuit 430 comprises four transistors M1˜M4. In addition, the gates ofthe transistors M2 and M3 are coupled to a common mode voltage levelV_(CM), the gates of the transistors M1 and M4 are respectively coupledto the control clock CK and inversed control clock CKN. Here, pleaserefer to FIG. 3, which is a diagram showing the control clock CK and theinversed control clock CKN.

Furthermore, the transistors M1 and M2 can be regarded as a differentialcircuit (or can be regarded as a sub-biasing module), where the sourcesof the transistors M1 and M2 are both coupled to a biasing currentsource 430, the drain of the transistor M1 is coupled to thepreamplifier 410, and the drain of the transistor M2 is coupled to theexternal voltage source V_(DD).

On the other hand, the transistors M3 and M4 can be regarded as anotherdifferential circuit (or can be regarded as another sub-biasing module),where the sources of the transistors M1 and M2 are both coupled to abiasing current source 432, the drain of the transistor M3 is coupled tothe preamplifier 410, and the drain of the transistor M4 is coupled tothe latching unit 420.

In addition, in order to make the entire circuit work correctly, thevoltage levels of the control clock CK, the inversed control clock CKN,and the common mode voltage level V_(CM) should be appropriately set. Inthis embodiment, when the control clock CK corresponds to a high logiclevel (e.g: rising edge), the voltage level of the control clock CK ishigher than the common mode voltage level V_(CM). Furthermore, thecontrol clock CK corresponds to a low logic level (e.g: falling edge),the voltage level of the control clock CK is lower than the common modevoltage level V_(CM).

For example, the high logic level of the control clock CK can be set asa voltage level 3.5V, the common mode voltage level V_(CM) can be set as0V, and the high logic level of the control clock CK can be set as avoltage level −3.5V. However, the above-mentioned voltage levels 3.5V,0V, and −3.5V are only utilized as an embodiment, not a limitation ofthe present invention.

In the following disclosure, the operations of the latch 400 will beillustrated.

First of all, when the control clock CK corresponds to a high logiclevel (such as at rising edge), for the differential circuit composed oftwo transistors M1 and M2, almost all of the current I3 provided by thebiasing current source 431 is transferred to the preamplifier 410 viathe transistor M1 because the control clock CK is much higher than thecommon mode voltage level V_(CM).

On the other hand, for the differential circuit composed of twotransistors M3 and M4, almost all of the current I4 provided by thebiasing current source 432 is transferred to the preamplifier 410 viathe transistor M3 because the common mode voltage level V_(CM) is muchhigher than the inversed control clock CKN.

In this embodiment, the preamplifier 410 comprises a transistor pair M7and M8 and two corresponding loads. After the current I3+I4 is inputtedinto the transistor pair M7 and M8, the transistor pair M7 and M8 startsto operate with the loads such that the preamplifier 410 performs anamplifying operation on the input signals Vin and Vip and then outputsthe amplified signals to the latching unit 420.

And then, when the control clock CK corresponds to a low logic level(e.g: falling edge), for the differential circuit composed of twotransistors M3 and M4, almost all of the current I4 provided by thebiasing current source 432 is transferred to the latching unit 420 viathe transistor M4 because the common mode voltage level V_(CM) is muchhigher than the inversed control clock CKN. Therefore, the latching unit420 operates to latch the signals transferred from the preamplifier 410and then outputs the latched signals.

From the above disclosure, it can be seen that the total biasing currentinputted into the preamplifier 410 is the sum of the two biasingcurrents I3+I4. In other words, if the currents I3 and I4 are the same(for example, they are both equal to the current I), the presentinvention biasing circuit 430 can provide the current 21 to thepreamplifier 410. In this way, the current can be double (it can have anequivalent effect of increasing the W/L ratio of the transistor).Furthermore, because the gate of the transistor M2 is coupled to thecommon mode voltage level V_(CM) such that it does not influence theparasitic capacitor of the transistor M1. This means that the parasiticcapacitor of the transistor M1 does not become larger. In other words,the load of the previous stage in not increased and the operationalfrequency of the latch 400 is not limited.

In other words, if the latch 400 needs to work in a high frequency andan additional biasing current is needed, the present invention canutilize the biasing current I4 as the additional biasing current (wherethe biasing current I3 can be the same). In this way, the W/L ratio ofthe transistor M1 does not need to be increased (this means that theparasitic capacitor is not increased, either). From the abovedisclosure, it can be seen that the present invention can achieve thepurpose of increasing the biasing current without increasing theparasitic capacitor. Therefore, the present invention 400 can no doubtwork in a higher frequency.

Please note that, in this embodiment, because the drain of thetransistor M2 is coupled to the external voltage source, when thecontrol clock CK corresponds to a low logic level (when the latchingunit 420 is working), only the biasing current I4 is transferred to thelatching unit 420 to use.

Please note that, the present invention does not limit the W/L ratios ofthe transistors M1˜M4 and the currents provided by the biasing currentsources 431 and 432. The circuit designer can adjust the W/L ratios ofthe transistors M1˜M4 and the currents provided by the biasing currentsources 431 and 432 according to his demands to allow the entire latch400 to work more efficiently. For example, when the latch 400 works in alower frequency, it means that the latching unit 420 needs to latch thesignal for a longer time. Obviously, the latching unit 420 needs alarger current. Therefore, the circuit designer can correspondinglydesign the current I4 as a larger current.

From the above disclosure, the operations and functions of the latch 400can be understood by those skilled in the art. In addition, thoseskilled in the art can easily utilize the latch 400 in a D-typeflip-flop, a frequency divider, or a PLL. As mentioned previously, theD-type flip-flop can be implemented by connecting two latches 400.Furthermore, the frequency divider having the devisor 2 can beimplemented by connecting the output Q′ to the input end D. Moreover, afrequency divider having a larger divisor can be implemented byconnecting several frequency dividers.

Please refer to FIG. 4, which is a diagram of a latch 500 of a firstembodiment according to the present invention. As shown in FIG. 4, inthis embodiment, the latch 500 is similar to the above-mentioned latch400. The difference between them is: in the biasing circuit 530, thedrain of the transistor M2 is coupled to the latching unit 520 insteadof the external voltage source V_(DD).

Therefore, in this embodiment, when the inversed control clock CKNcorresponds to a high logic level (the control clock CK corresponds to alow logic level), for the differential circuit composed of twotransistors M1 and M2, almost all of the current I3 provided by thebiasing current source 531 is transferred to the latching unit 520 viathe transistor M2 because the common mode voltage level V_(CM) is muchhigher than the control clock CK.

On the other hand, for the differential circuit composed of twotransistors M3 and M4, almost all of the current I4 provided by thebiasing current source 532 is transferred to the latching unit 520 viathe transistor M4 because the inversed control clock CKN is much higherthan the common mode voltage level V_(CM).

Therefore, the latching unit 520 starts to work to latch the signals andthen output the latched signals.

From the above, it can be seen that when the latching unit 520 works,the current passing through the transistor M2 is transferred to thelatching unit 520. In other words, in this embodiment, the total biasingcurrent inputted to the preamplifier 510 and the latching unit 520 isequal to the sum of the currents I3 and I4.

Similarly, the present invention does not limit the W/L ratios of thetransistors M1˜M4 and the currents provided by the biasing currentsources 531 and 532. The circuit designer can adjust the W/L ratios ofthe transistors M1˜M4 and the currents provided by the biasing currentsources 531 and 532 according to his demands (for example, the frequencywhich the latch 500 work at) to allow the entire latch 400 to work moreefficiently.

Please refer to FIG. 5, which is a diagram of a latch 600 of a thirdembodiment according to the present invention. As shown in FIG. 5, thelatch 600 adds two AC couple circuits 640 and 650. The AC couple circuit640 is coupled between the control clock CK and the preamplifier 610.The AC couple circuit 650 is coupled between the inversed clock CKN andthe latching unit 620.

Each of the AC couple circuits 640 and 650 comprises a resistor and acapacitor, which is parallel to the resistor as shown in FIG. 5. In thisembodiment, the AC couple circuits 640 and 650 are utilized to make theentire circuit work at a best operational point. The operations and thefunctions of the AC couple circuits 640 and 650 are well known, and thusomitted here.

Please refer to FIG. 6, which is a diagram of a latch 700 of a fourthembodiment according to the present invention. As shown in FIG. 6, inthe biasing circuit 730, adjustable current sources 731 and 732 areutilized instead of the above-mentioned fixed current sources. In thisway, the circuit designer can easily change the currents provided by theadjustable current sources 731 and 732 such that the latch 700 can havebetter performance when it works at different frequencies.

In contrast to the prior art, the present invention does not need toadjust the W/L ratio of the inner transistors or to increase V_(GS) ofthe inner transistors in order to increase the biasing current.Therefore, the present invention latch can prevent from the parasiticcapacitor problem and can be operated in a high frequency.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention should not be limited to the specific constructionand arrangement shown and described, since various other modificationsmay occur to those ordinarily skilled in the art.

1. A latch comprising: an amplifying circuit, for receiving a firstbiasing current in a first state to amplify an input signal to generatean amplified signal; a latching unit, coupled to the amplifying circuit,for latching the amplified signal and for receiving a second biasingcurrent in a second state to output the amplified signal; and a biasingcircuit, coupled to the amplifying circuit and the latching unit, forproviding the first biasing current to the amplified circuit in thefirst state and for providing the second biasing current to the latchingunit in the second state, the biasing circuit comprising: a firstbiasing module, coupled to the amplifying circuit, for providing a thirdbiasing current to the amplifying circuit in the first state; and asecond biasing module, coupled to the amplifying circuit and thelatching unit, for providing a fourth biasing current to the amplifyingcircuit in the first state and providing the fourth as the secondbiasing current to the latching unit in the second state; wherein thefirst biasing current is equal to a sum of the third biasing current andthe fourth biasing current; wherein the first biasing module comprises:a first biasing current source, for providing the third biasing current:a first transistor, having a control end, a first end, and a second end,the control end coupled to a first clock, the first end coupled to theamplifying circuit, and the second end coupled to the first currentsource; and a second transistor, having a control end, a first end, anda second end, the control end coupled to a common voltage level, and thesecond end coupled to the first current source: and the second biasingmodule comprises: a second biasing current source, for providing thefourth biasing current; a third transistor, having a control end, afirst end, and a second end, the control end coupled to the common modevoltage level, the first end coupled to the amplifying circuit, and thesecond end coupled to a second current source; and a fourth transistor,having a control end, a first end, and a second end, the control endcoupled to a second clock, and the first end coupled to the latchingunit, and the second end coupled to the second current source.
 2. Thelatch of claim 1, wherein the first clock is an inversed signal of thesecond clock.
 3. The latch of claim 1, wherein the first biasing currentsource is an adjustable current source.
 4. The latch of claim 1, whereinthe second biasing current source is an adjustable current source. 5.The latch of claim 1, further comprising: an AC couple circuit, coupledto the biasing circuit, for determining an operational point of thelatch.
 6. The latch of claim 5, wherein the AC couple circuit comprises:a resistor, coupled to the biasing circuit; and a capacitor, coupledbetween the biasing circuit and a common mode voltage level.
 7. A latchcomprising: an input circuit, for receiving an input signal andgenerating an output signal according to the input signal and an inputreference current; an output circuit, coupled to the input circuit, forreceiving the output signal and outputting the output signal accordingto an output reference current; and a current generating circuit,coupled to the input circuit and the output circuit, for generating theinput reference current to the input circuit according to a first logiclevel of a clock signal, and for generating the output reference currentto the output circuit according to a second logic level of the clocksignal, the current generating circuit comprising: a first currentgenerating unit, for providing a first current to the input circuit whenthe clock signal corresponds to the first logic level, wherein the firstcurrent is a part of the input reference current; and a second currentgenerating unit, for providing a second current to the input circuitwhen the clock signal corresponds to the first logic level, and forproviding the second current to the output circuit when the clock signalcorresponds to the second logic level, wherein the second current is apart of the input reference current, and the second current is equal tothe output reference current or is a part of the output referencecurrent; wherein the first current generating unit comprises: a firsttransistor pair, coupled to the input circuit, respectively forreceiving the clock signal and a reference signal; and a first currentsource, coupled to the first transistor pair, for providing the firstcurrent: wherein the first transistor establishes a first conductingpath when the clock signal corresponds to the first logic level; and thefirst current source provides the first current to the input circuit viathe first conducting path.
 8. The latch of claim 7, wherein the inputcircuit comprises: a transistor pair, for receiving the input signal;and a plurality of loading units, coupled to the transistor pair, fordetermining the output signal according to the input reference current;wherein the input signal is a differential signal.
 9. The latch of claim7, wherein the output circuit comprises: a cross-coupled transistorpair, coupled to the input circuit and the second current generatingunit, for receiving the input signal, latching the output signal,outputting the output signal according to the output reference currentwhen the clock signal corresponds to the second logic level.
 10. Thelatch of claim 7, wherein an amplitude of the reference signal is lowerthan the first logic level, and higher than the second logic level. 11.The latch of claim 7, wherein the first current generating unit providesthe first current to the output circuit when the clock signalcorresponds to the second logic level, and the first current is a partof the output reference current.
 12. The latch of claim 11, wherein thefirst transistor establishes a second conducting path when the clocksignal corresponds to the second logic level, the first current sourceprovides the first current to the output circuit via the secondconducting path.
 13. The latch of claim 12, wherein an amplitude of thereference signal is lower than the first logic level, and higher thanthe second logic level.
 14. The latch of claim 7, wherein the secondcurrent generating unit comprises: a second transistor pair, coupled tothe input circuit and the output circuit, respectively for receiving aninversed signal of the clock signal and a reference signal; and a secondcurrent source, coupled to the second transistor pair, for providing thesecond current; wherein the second transistor establishes a thirdconducting path when the clock signal corresponds to the first logiclevel, the second current source provides the second current to theinput circuit via the third conducting path, and the second transistorestablishes a fourth conducting path when the clock signal correspondsto the second logic level, the second current source provides the secondcurrent to the output circuit via the fourth conducting path.
 15. Thelatch of claim 14, wherein an amplitude of reference signal is lowerthan the first logic level, and higher than the second logic level. 16.The latch of claim 7, wherein at least one of the first currentgenerating unit and the second current generating unit comprises anadjustable current source.
 17. The latch of claim 7, wherein the firstcurrent is different from the second current.
 18. The latch of claim 7,further comprising: an AC couple circuit, coupled to the currentgenerating circuit; wherein the clock signal is inputted into thecurrent generating circuit through the AC couple circuit.
 19. A latchcomprising: an amplifying circuit, for receiving a first biasing currentin a first state to amplify an input signal to generate an amplifiedsignal; a latching unit, coupled to the amplifying circuit, for latchingthe amplified signal and for receiving a second biasing current in asecond state to output the amplified signal; and a biasing circuit,coupled to the amplifying circuit and the latching unit, for providingthe first biasing current to the amplified circuit in the first stateand for providing the second biasing current to the latching unit in thesecond state, the biasing circuit comprising: a first biasing module,coupled to the amplifying circuit, for providing a third biasing currentto the amplifying circuit in the first state; and a second biasingmodule, coupled to the amplifying circuit, for providing a fourthbiasing current to the amplifying circuit; wherein the first biasingcurrent is equal to a sum of the third biasing current and the fourthbiasing current; and wherein the first biasing module and the secondbiasing module are both coupled to the latching unit, for respectivelyproviding a fifth biasing current and a sixth current to the latchingunit; and the second biasing current is equal to a sum of the fifthbiasing current and the sixth biasing current.
 20. The latch of claim19, wherein the first biasing module comprises: a first biasing currentsource, for providing the third biasing current; a first transistor,having a control end, a first end, and a second end, the control endcoupled to a first clock, the first end coupled to the amplifyingcircuit, and the second end coupled to the first current source; and asecond transistor, having a control end, a first end, and a second end,the control end coupled to a common mode voltage level, the first endcoupled to the latching unit, and the second end coupled to the firstcurrent source; and the second biasing module comprises: a secondbiasing current source, for providing the fourth biasing current; athird transistor, having a control end, a first end, and a second end,the control end coupled to the common mode voltage level, the first endcoupled to the amplifying circuit, and the second end coupled to asecond current source; and a second transistor, having a control end, afirst end, and a second end, the control end coupled to a second clock,and the first end coupled to the latching unit, and the second endcoupled to the second current source.
 21. The latch of claim 20, whereinat least one of the first biasing current source and the second biasingcurrent source is an adjustable current source.
 22. The latch of claim19, further comprising: an AC couple circuit, coupled to the biasingcircuit, for determining an operational point of the latch.
 23. Thelatch of claim 22, wherein the AC couple circuit comprises: a resistor,coupled to the biasing circuit; and a capacitor, coupled between thebiasing circuit and a common mode voltage level.